Metal-oxide-semiconductor (MOS) devices are basic building elements in integrated circuits. A conventional MOS device typically has a gate electrode comprising polysilicon doped with p-type or n-type impurities, using doping operations such as ion implantation or thermal diffusion. It is preferable to adjust the work function of the gate electrode to the band-edge of the silicon; that is, for an NMOS device, adjusting the work function close to the conduction band, and for a PMOS device, adjusting the work function close to the valence band. Adjusting the work function of the polysilicon gate electrode can be achieved by selecting appropriate impurities.
MOS devices with polysilicon gate electrodes exhibit carrier depletion effect, which is also referred to as a poly depletion effect. The poly depletion effect occurs when applied electrical fields sweep away carriers from regions close to gate dielectrics, forming depletion layers. In an n-doped polysilicon layer, the depletion layer includes ionized non-mobile donor sites, whereas in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult for an inversion layer to be created at the surface of the semiconductor.
The use of thin gate dielectrics tends to make the carrier depletion effect worse. With thin gate dielectrics, the depletion layer in the polysilicon gate becomes more significant in thickness when compared to the thickness of the thin gate dielectrics, and thus device performance degradation suffers. As a result, the carrier depletion effect in the gate electrodes limits device scalability by imposing a lower bound on how much the effective gate dielectric thickness can be reduced.
A further problem is that with the thin gate oxides, gate leakage currents are increased. Therefore, high-k dielectrics are used to reduce gate leakage currents. However, high-k dielectric materials are not compatible with polysilicon gates due to Fermi level pinning.
The poly depletion effects and high-k incompatibility problems may be solved by forming metal gate electrodes or metal silicide gate electrodes, wherein preferably, the metallic gates used in NMOS devices and PMOS devices also have band-edge work functions. Currently, materials suitable for forming gate electrodes of NMOS devices have been found. However, for PMOS devices, even though metallic materials having band-edge work functions are available, these materials have poor thermal stability. When exposed to the high temperatures of the front-end-of-line processes, the work functions of these metallic materials shift, for example, toward the mid-gap level. The performance of the resulting PMOS devices is thus adversely affected. In addition, after exposed to the high temperatures, the capacitance-equivalent-thickness (CET) of these high-work-function metals becomes higher than that of the metals having low work functions.
Iridium and platinum are among the most promising metals with high work functions. However, platinum is not process friendly, and it is hard to pattern a platinum layer as a gate using conventional reactive ion etch (RIE). Iridium, on the other hand, is process friendly. However, it has been found that a pure iridium gate exhibits serious diffusion problem, wherein iridium penetrates through high-k materials after 1000° C. rapid thermal activation.
Accordingly, what is needed in the art is a semiconductor structure and respective formation methods that take advantage of the benefits associated with band-edge work functions while at the same time overcoming the deficiencies of the prior art.